7546 datasheet(28/95 Pages) RENESAS

28 / 95 page

7546 Group

Rev.1.21

Nov 15, 2006

page 28 of 93

REJ03B0160-0121

(4) Pulse width measurement mode

In the pulse width measurement mode, the pulse width of the sig-

nal input to P14/CNTR0 pin is measured.

The operation of Timer X can be controlled by the level of the sig-

nal input from the CNTR0 pin.

When the CNTR0 active edge switch bit is “0”, the signal selected

by the timer X count source selection bit is counted while the input

signal level of CNTR0 pin is “H”. The count is stopped while the

pin is “L”. Also, when the CNTR0 active edge switch bit is “1”, the

signal selected by the timer X count source selection bit is

counted while the input signal level of CNTR0 pin is “L”. The count

is stopped while the pin is “H”.

Timer X can stop counting by setting “1” to the timer X count stop

bit in any mode.

Also, when Timer X underflows, the timer X interrupt request bit is

set to “1”.

Note on Timer X is described below;

s Note on Timer X

(1) CNTR0 interrupt active edge selection-1

CNTR0 interrupt active edge depends on the CNTR0 active edge

switch bit.

When this bit is “0”, the CNTR0 interrupt request bit is set to “1” at

the falling edge of CNTR0 pin input signal. When this bit is “1”, the

CNTR0 interrupt request bit is set to “1” at the rising edge of

CNTR0 pin input signal.

(2) CNTR0 interrupt active edge selection-2

According to the setting value of CNTR0 active edge switch bit,

the interrupt request bit may be set to “1”.

When not requiring the interrupt occurrence synchronized with

these setting, take the following sequence.

➀ Set the corresponding interrupt enable bit to “0” (disabled).

➁ Set the active edge switch bit.

➂ Set the corresponding interrupt request bit to “0” after 1 or more

instructions have been executed.

➃ Set the corresponding interrupt enable bit to “1” (enabled).

Fig. 23 Structure of timer X mode register

Fig. 24 Timer count source set register

Timer X mode register

(TXM : address 002B16, initial value: 0016)

CNTR0 active edge switch bit

0 : Interrupt at falling edge

Count at rising edge

(in event counter mode)

1 : Interrupt at rising edge

Count at falling edge

(in event counter mode)

Timer X operating mode bits

b1 b0

0 : Timer mode

1 : Pulse output mode

0 : Event counter mode

1 : Pulse width measurement mode

Not used (return “0” when read)

Timer X count stop bit

0 : Count start

1 : Count stop

P03/TXOUT output valid bit

0 : Output invalid (I/O port)

1 : Output valid (Inverted CNTR0 output)

Timer X count source selection bits

b1 b0

0 : f(XIN)/16

1 : f(XIN)/2

0 : f(XIN) (Note 1)

1 : Not available

Notes 1: f(XIN) can be used as timer X count source when using

a ceramic resonator or on-chip oscillator.

Do not use it at RC oscillation.

2: On-chip oscillator can be used when the on-chip oscillator

is enabled by bit 3 of CPUM.

Timer count source set register

(TCSS : address 002A16, initial value: 0016)

Timer B count source selection bits

b7 b6 b5

0 : f(XIN)/16

1 : f(XIN)/2

0 : f(XIN)/32

1 : f(XIN)/64

0 : f(XIN)/128

1 : f(XIN)/256

0 : Timer A underflow

1 : Not available

Timer A count source selection bits

b4 b3 b2

0 : f(XIN)/16

1 : f(XIN)/2

0 : f(XIN)/32

1 : f(XIN)/64

0 : f(XIN)/128

1 : f(XIN)/256

0 : On-chip oscillator output (Note 2)

1 : Not available

7546 Datasheet(PDF) 28 Page - Renesas Technology Corp

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