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M30201 Datasheet(PDF) 46 Page - Renesas Technology Corp |
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M30201 Datasheet(HTML) 46 Page - Renesas Technology Corp |
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46 / 172 page ![]() Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Watchdog Timer 45 Write to the watchdog timer start register (address 000E16) RESET Watchdog timer interrupt request Watchdog timer Set to “7FFF16” 1/128 1/16 “CM07 = 0” “WDC7 = 1” “CM07 = 0” “WDC7 = 0” “CM07 = 1” BCLK 1/2 Prescaler Figure 1.34. Block diagram of watchdog timer Watchdog Timer The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. When XIN is selected for the BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by 16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register (address 000F16). When XIN is selected in BCLK Watchdog timer cycle = When XCIN is selected in BCLK Watchdog timer cycle = For example, when BCLK is 10MHz and the prescaler division ratio is set to 16, the watchdog timer cycle is approximately 52.4 ms. The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by writing to the watchdog timer start register (address 000E16). In stop mode and wait mode the watchdog timer and prescaler are stopped. Counting is resumed from the held value when the modes are released. Figure 1.34 shows the block diagram of the watchdog timer. Figure 1.35 shows the watchdog timer-related registers. Prescaler division ratio (16 or 128) x watchdog timer count (32768) BCLK Prescaler division ratio (2) x watchdog timer count (32768) BCLK |
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