M30201 datasheet(80/172 Pages) RENESAS

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Mitsubishi microcomputers

M30201 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Serial I/O

(1) Clock synchronous serial I/O mode

The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. (See Table

1.25.) Figure 1.65 shows the UART0 transmit/receive mode register.

Table 1.25. Specifications of clock synchronous serial I/O mode

Specification

• Transfer data length: 8 bits

• When internal clock is selected (bit 3 at address 03A016 = “0”) : fi/ 2(n+1) (Note 1)

fi = f1, f8, f32, fc

• When external clock is selected (bit 3 at address 03A016 = “1”) : Input from CLK0 pin

• To start transmission, the following requirements must be met:

_ Transmit enable bit (bit 0 at address 03A516) = “1”

_ Transmit buffer empty flag (bit 1 at addresses 03A516) = “0”

• Furthermore, if external clock is selected, the following requirements must also be met:

_ CLK0 polarity select bit (bit 6 at address 03A416) = “0”: CLK0 input level = “H”

_ CLK0 polarity select bit (bit 6 at address 03A416) = “1”: CLK0 input level = “L”

• To start reception, the following requirements must be met:

_ Receive enable bit (bit 2 at address 03A516) = “1”

_ Transmit enable bit (bit 0 at address 03A516) = “1”

_ Transmit buffer empty flag (bit 1 at address 03A516) = “0”

• Furthermore, if external clock is selected, the following requirements must also be met:

_ CLK0 polarity select bit (bit 6 at address 03A416) = “0”: CLK0 input level = “H”

_ CLK0 polarity select bit (bit 6 at address 03A416) = “1”: CLK0 input level = “L”

• When transmitting

_ Transmit interrupt cause select bit (bit 0 at address 03B016) = “0”: Interrupts re-

quested when data transfer from UART0 transfer buffer register to UART0 transmit

_ Transmit interrupt cause select bit (bit 0 at address 03B016) = “1”: Interrupts re-

quested when data transmission from UART0 transfer register is completed

• When receiving

_ Interrupts requested when data transfer from UART0 receive register to UART0

receive buffer register is completed

• Overrun error (Note 2)

This error occurs when the next data is ready before contents of UART0 receive

buffer register are read out

• CLK polarity selection

Whether transmit data is output/input at the rising edge or falling edge of the trans-

fer clock can be selected

• LSB first/MSB first selection

Whether transmission/reception begins with bit 0 or bit 7 can be selected

• Continuous receive mode selection

Reception is enabled simultaneously by a read from the receive buffer register

• Transfer clock output from multiple pins selection

UART0 transfer clock can be chosen by software to be output from one of the two

pins set

Clock synchronous serial I/O mode

Item

Transfer data format

Transfer clock

Transmission start

condition

Reception start

conditio

Interrupt request

generation timing

Error detection

Select function

Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator.

Note 2: If an overrun error occurs, the UART0 receive buffer will have the next data written in. Note also that the

UART0 receive interrupt request bit does not change.

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