M30201 datasheet(85/172 Pages) RENESAS

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Mitsubishi microcomputers

M30201 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Serial I/O

Item

Specification

• Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected

• Start bit: 1 bit

• Parity bit: Odd, even, or nothing as selected

• Stop bit: 1 bit or 2 bits as selected

• When internal clock is selected (bit 3 at addresses 03A016, 03A816 = “0”) :

fi/16(n+1) (Note 1) fi = f1, f8, f32, fC

• When external clock is selected (bit 3 at addresses 03A016=“1”) :

fEXT/16(n+1) (Note 1) (Note 2)

• To start transmission, the following requirements must be met:

- Transmit enable bit (bit 0 at addresses 03A516, 03AD16) = “1”

- Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = “0”

• To start reception, the following requirements must be met:

- Receive enable bit (bit 2 at addresses 03A516, 03AD16) = “1”

- Start bit detection

• When transmitting

- Transmit interrupt cause select bits (bits 0,1 at address 03B016) = “0”:

Interrupts requested when data transfer from UARTi transfer buffer register

to UARTi transmit register is completed

- Transmit interrupt cause select bits (bits 0, 1 at address 03B016) = “1”:

Interrupts requested when data transmission from UARTi transfer register is

completed

• When receiving

- Interrupts requested when data transfer from UARTi receive register to

UARTi receive buffer register is completed

• Overrun error (Note 3)

This error occurs when the next data is ready before contents of UARTi

receive buffer register are read out

• Framing error

This error occurs when the number of stop bits set is not detected

• Parity error

This error occurs when if parity is enabled, the number of 1’s in parity and

character bits does not match the number of 1’s set

• Error sum flag

This flag is set (= 1) when any of the overrun, framing, and parity errors is

encountered

• Sleep mode selection

This mode is used to transfer data to and from one of multiple slave micro-

computers

(2) Clock asynchronous serial I/O (UART) mode

The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer

data format. (See Table 1.27.) Figure 1.79 shows the UARTi transmit/receive mode register.

Table 1.27. Specifications of UART Mode

Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UART bit rate generator.

Note 2: fEXT is input from the CLK0 pin. Since UART1 does not have this pin, cannot select external clock.

Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that

the UARTi receive interrupt request bit does not change.

Clock asynchronous serial I/O (UART) mode

Transfer data format

Transfer clock

Transmission start

condition

Reception start condi-

tion

Interrupt request gen-

eration timing

Error detection

Select function

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