M30201 datasheet(78/172 Pages) RENESAS

78 / 172 page

Mitsubishi microcomputers

M30201 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Serial I/O

Figure 1.72. Serial I/O-related registers (2)

UARTi transmit/receive mode register

Symbol

Address

When reset

UiMR(i=0,1)

03A016, 03A816

0016

b7 b6

b1 b0

Bit name

Bit

symbol

Must be fixed to 001

0 0 0 : Serial I/O invalid

0 1 0 : Inhibited

0 1 1 : Inhibited

1 1 1 : Inhibited

b2 b1 b0

CKDIR

SMD1

SMD0

Serial I/O mode select bit

(Note 1)

SMD2

Internal/external clock

select bit (Note 2)

STPS

PRY

PRYE

SLEP

Parity enable bit

0 : Internal clock (Note 3)

1 : External clock (Note 4)

Stop bit length select bit

Odd/even parity select bit

Sleep select bit

0 : One stop bit

1 : Two stop bits

0 : Parity disabled

1 : Parity enabled

0 : Sleep mode deselected

1 : Sleep mode selected

1 0 0 : Transfer data 7 bits long

1 0 1 : Transfer data 8 bits long

1 1 0 : Transfer data 9 bits long

0 0 0 : Serial I/O invalid

0 1 0 : Inhibited

0 1 1 : Inhibited

1 1 1 : Inhibited

b2 b1 b0

0 : Internal clock (Note 3)

1 : External clock (Note 4)

Invalid

Valid when bit 6 = “1”

0 : Odd parity

1 : Even parity

Invalid

Must always be “0”

Function

(During UART mode)

Function

(During clock synchronous

serial I/O mode)

UARTi transmit/receive control register 0

Symbol

Address

When reset

UiC0(i=0,1)

03A416, 03AC16

0816

b2 b1

Function

(During UART mode)

Function (Note)

(During clock synchronous

serial I/O mode)

TXEPT

CLK1

CLK0

NCH

CKPOL

BRG count source

select bit

Transmit register empty

flag

0 : Transmit data is output at

falling edge of transfer clock

and receive data is input at

rising edge

1 : Transmit data is output at

rising edge of transfer clock

and receive data is input at

falling edge

CLK polarity select bit

Data output select bit

0 0 : f1 is selected

0 1 : f8 is selected

1 0 : f32 is selected

1 1 : fc is selected

b1 b0

0 : LSB first

1 : MSB first

0 : Data present in transmit

1 : No data present in transmit

completed)

0 : TXDi pin is CMOS output

1 : TXDi pin is N-channel

open-drain output

UFORM Transfer format select bit

0 0 : f1 is selected

0 1 : f8 is selected

1 0 : f32 is selected

1 1 : fc is selected

b1 b0

0 : Data present in transmit register

(during transmission)

1 : No data present in transmit

0: TXDi pin is CMOS output

1: TXDi pin is N-channel

open-drain output

Must always be “0”

Bit name

Bit

symbol

Must always be “0”

Note: UART1 cannot be used in clock synchronous serial I/O.

Note 1: UART1 cannot be used in clock synchronous serial I/O.

Note 2: UART1 can use only internal clock. Must set this bit to “1”.

Note 3: Set the corresponding port direction register to “1” (output mode).

Note 4: Set the corresponding port direction register to “0” (input mode).

Set this bit to “0”.

Set this bit to “1”.

M30201 Datasheet(PDF) 78 Page - Renesas Technology Corp

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