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HD64F36037 Datasheet(PDF) 35 Page - Renesas Technology Corp |
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HD64F36037 Datasheet(HTML) 35 Page - Renesas Technology Corp |
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35 / 592 page  Section 1 Overview Rev. 4.00 Mar. 15, 2006 Page 3 of 556 REJ09B0026-0400 1.2 Internal Block Diagram POR and LVD*3 P10 P11 P12 P14/ IRQ0 P15/ IRQ1/TMIB1 P16/ IRQ2 P17/ IRQ3/TRGV P57 P56 P55/ WKP5/ADTRG P54/ WKP4 P53/ WKP3 P52/ WKP2 P51/ WKP1 P50/ WKP0 P20/SCK3 P21/RXD P22/TXD P23 P24 P87 P86 P85 CPU H8/300H Data bus (lower) System clock generator Internal oscillator ROM Subtimer Timer Z Timer V A/D converter RAM TinyCAN SCI3 SCI3_2*1 Watchdog timer SSU P67/FTIOD1 P66/FTIOC1 P65/FTIOB1 P64/FTIOA1 P63/FTIOD0 P62/FTIOC0 P61/FTIOB0 P60/FTIOA0 P76/TMOV P75/TMCIV P74/TMRIV P72/TXD_2*2 P71/RXD_2*2 P70/SCK3_2*2 P90/ SCS P91/SSCK P92/SSO P93/SSI P94 P95 P96/HRxD P97/HTxD Data bus (upper) Address bus Notes: 1. The SCI3_2 is incorporated only in the H8/36057. 2. The SCK3_2, RXD_2, and TXD_2 pins are not multiplexed in the H8/36037. 3. POR and LVD function is incorporated in the H8/36057G and H8/36037G. Port B Timer B1 Figure 1.1 Internal Block Diagram of F-ZTAT TM and Masked ROM Versions |
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