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HD64F36037 Datasheet(PDF) 25 Page - Renesas Technology Corp

Part # HD64F36037
Description  Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series
PDF  592 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F36037 Datasheet(HTML) 25 Page - Renesas Technology Corp

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Rev. 4.00 Mar. 15, 2006 Page xxv of xxxii
Figure 14.5 Example of SCI3 Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit) ........................................................................... 272
Figure 14.6 Sample Serial Transmission Data Flowchart (Asynchronous Mode)...................... 273
Figure 14.7 Example of SCI3 Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit) ........................................................................... 274
Figure 14.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (1)...................... 276
Figure 14.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (2)...................... 277
Figure 14.9 Data Format in Clocked Synchronous Communication .......................................... 278
Figure 14.10 Example of SCI3 Transmission in Clocked Synchronous Mode........................... 279
Figure 14.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode) ................ 280
Figure 14.12 Example of SCI3 Reception in Clocked Synchronous Mode................................ 281
Figure 14.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)...................... 282
Figure 14.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
(Clocked Synchronous Mode)............................................................................... 284
Figure 14.15 Example of Inter-Processor Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A) .......................................... 286
Figure 14.16 Sample Multiprocessor Serial Transmission Flowchart ........................................ 287
Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 288
Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 289
Figure 14.18 Example of SCI3 Reception Using Multiprocessor Format
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................. 290
Figure 14.19 Receive Data Sampling Timing in Asynchronous Mode ...................................... 293
Section 15 Controller Area Network for Tiny (TinyCAN)
Figure 15.1 TinyCAN Block Diagram........................................................................................ 296
Figure 15.2 Standard Format and Extended Format ................................................................... 319
Figure 15.3 Message Data Configuration ................................................................................... 323
Figure 15.4 Reset Clearing Flowchart ........................................................................................ 324
Figure 15.5 CAN Bit Configuration ........................................................................................... 325
Figure 15.6 Transmission Request Flowchart............................................................................. 327
Figure 15.7 Internal Arbitration at Transmission Caused by TXCR/TXPR Setting................... 329
Figure 15.8 Internal Arbitration at Reception Caused by CAN Bus Arbitration Loss
(MBn in TXCR = 0 and DART = 0)........................................................................ 330
Figure 15.9 Internal Arbitration at Reception Caused by CAN Bus Arbitration Loss
(MBn in TXCR = 1) ................................................................................................ 331
Figure 15.10 Internal Arbitration at Reception Caused by CAN Bus Arbitration Loss
(DART = 1) ........................................................................................................... 332
Figure 15.11 Internal Arbitration at Error Detection (MBn in TXCR = 0 and DART = 0)........ 333
Figure 15.12 Internal Arbitration at Error Detection (MBn in TXCR = 1)................................. 334
Figure 15.13 Internal Arbitration at Error Detection (DART = 1).............................................. 335
Figure 15.14 Message Reception Flowchart............................................................................... 336



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