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HD64F36037 Datasheet(PDF) 24 Page - Renesas Technology Corp |
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HD64F36037 Datasheet(HTML) 24 Page - Renesas Technology Corp |
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24 / 592 page ![]() Rev. 4.00 Mar. 15, 2006 Page xxiv of xxxii Figure 12.36 Input Capture Buffer Operation............................................................................. 221 Figure 12.37 Example of Buffer Operation Setting Procedure................................................... 222 Figure 12.38 Example of Buffer Operation (1) (Buffer Operation for Output Compare Register) ................................................. 223 Figure 12.39 Example of Compare Match Timing for Buffer Operation ................................... 224 Figure 12.40 Example of Buffer Operation (2) (Buffer Operation for Input Capture Register) ...................................................... 225 Figure 12.41 Input Capture Timing of Buffer Operation............................................................ 226 Figure 12.42 Buffer Operation (3) (Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1)............ 227 Figure 12.43 Buffer Operation (4) (Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1)............ 228 Figure 12.44 Example of Output Disable Timing of Timer Z by Writing to TOER .................. 229 Figure 12.45 Example of Output Disable Timing of Timer Z by External Trigger.................... 230 Figure 12.46 Example of Output Inverse Timing of Timer Z by Writing to TFCR ................... 230 Figure 12.47 Example of Output Inverse Timing of Timer Z by Writing to POCR................... 231 Figure 12.48 IMF Flag Set Timing when Compare Match Occurs ............................................ 232 Figure 12.49 IMF Flag Set Timing at Input Capture .................................................................. 233 Figure 12.50 OVF Flag Set Timing............................................................................................ 233 Figure 12.51 Status Flag Clearing Timing.................................................................................. 234 Figure 12.52 Contention between TCNT Write and Clear Operations....................................... 235 Figure 12.53 Contention between TCNT Write and Increment Operations ............................... 236 Figure 12.54 Contention between GR Write and Compare Match............................................. 237 Figure 12.55 Contention between TCNT Write and Overflow................................................... 238 Figure 12.56 Contention between GR Read and Input Capture.................................................. 239 Figure 12.57 Contention between Count Clearing and Increment Operations by Input Capture .................................................................................................................. 240 Figure 12.58 Contention between GR Write and Input Capture................................................. 241 Figure 12.59 When Compare Match and Bit Manipulation Instruction to TOCR Occur at the Same Timing ......................................................................................................... 243 Section 13 Watchdog Timer Figure 13.1 Block Diagram of Watchdog Timer ........................................................................ 245 Figure 13.2 Watchdog Timer Operation Example...................................................................... 249 Section 14 Serial Communication Interface 3 (SCI3) Figure 14.1 Block Diagram of SCI3........................................................................................... 253 Figure 14.2 Data Format in Asynchronous Communication ...................................................... 270 Figure 14.3 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)............. 270 Figure 14.4 Sample SCI3 Initialization Flowchart ..................................................................... 271 |
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