HD64F36037 datasheet(75/592 Pages) RENESAS

75 / 592 page

Section 2 CPU

Rev. 4.00 Mar. 15, 2006 Page 43 of 556

REJ09B0026-0400

The timer is counting, so the value read is not necessarily the same as the value in the timer load

modified value may be written to the timer load register.

Read

Write

Count clock

Timer counter

Timer load register

Reload

Internal data bus

Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same

Address

Example 2: The BSET instruction is executed for port 5.

P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at

P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level

signal at P50 with a BSET instruction is shown below.

• Prior to executing BSET instruction

P57

P56

P55

P54

P53

P52

P51

P50

Input/output

Input

Output

Pin state

Low

level

High

level

Low

level

Low

level

Low

level

Low

level

Low

level

Low

level

PCR5

PDR5

• BSET instruction executed instruction

BSET

#0,

@PDR5

The BSET instruction is executed for port 5.

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