SH7261 datasheet(467/1348 Pages) RENESAS

467 / 1348 page

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 Sep. 07, 2007 Page 435 of 1312

REJ09B0320-0200

12.3.15

Timer Synchronous Register (TSYR)

TSYR is an 8-bit readable/writable register that selects independent operation or synchronous

operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when

the corresponding bit in TSYR is set to 1.

Bit:

Initial value:

R/W:

7654321

00000000

R/W

SYNC4 SYNC3

———

SYNC2 SYNC1 SYNC0

Bit

Bit Name

Initial

Value

R/W

Description

SYNC4

R/W

SYNC3

R/W

Timer Synchronous operation 4 and 3

These bits are used to select whether operation is

independent of or synchronized with other channels.

When synchronous operation is selected, the TCNT

synchronous presetting of multiple channels, and

synchronous clearing by counter clearing on another

channel, are possible.

To set synchronous operation, the SYNC bits for at

least two channels must be set to 1. To set

synchronous clearing, in addition to the SYNC bit, the

TCNT clearing source must also be set by means of

bits CCLR0 to CCLR2 in TCR.

0: TCNT_4 and TCNT_3 operate independently (TCNT

presetting/clearing is unrelated to other channels)

1: TCNT_4 and TCNT_3 performs synchronous

operation

TCNT synchronous presetting/synchronous clearing

is possible

5 to 3

—

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

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