SH7261 datasheet(474/1348 Pages) RENESAS

474 / 1348 page

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 Sep. 07, 2007 Page 442 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

TOCL

R/(W)*

TOC Register Write Protection*

This bit selects the enable/disable of write access to the

TOCS, OLSN, and OLSP bits in TOCR1.

0: Write access to the TOCS, OLSN, and OLSP bits is

enabled

1: Write access to the TOCS, OLSN, and OLSP bits is

disabled

TOCS

R/W

TOC Select

This bit selects either the TOCR1 or TOCR2 setting to

be used for the output level in complementary PWM

mode and reset-synchronized PWM mode.

0: TOCR1 setting is selected

1: TOCR2 setting is selected

OLSN

R/W

Output Level Select N*

This bit selects the reverse phase output level in reset-

synchronized PWM mode/complementary PWM mode.

See table 12.30.

OLSP

R/W

Output Level Select P*

This bit selects the positive phase output level in reset-

synchronized PWM mode/complementary PWM mode.

See table 12.31.

Notes: 1. This bit can be set to 1 only once after a power on reset. After 1 is written, 0 cannot be

written to the bit.

2. Setting the TOCL bit to 1 prevents accidental modification when the CPU goes out of

control.

3. Clearing the TOCS bit to 0 makes this bit setting valid.

Table 12.30 Output Level Select Function

Bit 1

Function

Compare Match Output

OLSN

Initial Output

Active Level

Up Count

Down Count

High level

Low level

High level

Low level

High level

Low level

High level

Note:

The reverse phase waveform initial output value changes to active level after elapse of the

dead time after count start.

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