SH7261 datasheet(473/1348 Pages) RENESAS

473 / 1348 page

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 Sep. 07, 2007 Page 441 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

OE3B

R/W

Master Enable TIOC3B

This bit enables/disables the TIOC3B pin MTU2 output.

0: MTU2 output is disabled (inactive level)*

1: MTU2 output is enabled

Note:

The inactive level is determined by the settings in timer output control registers 1 and 2

(TOCR1 and TOCR2). For details, refer to section 12.3.19, Timer Output Control

Set these bits to 1 to enable MTU2 output in other than complementary PWM or reset-

synchronized PWM mode. If these bits are set to 0, low level is output.

12.3.19

Timer Output Control Register 1 (TOCR1)

TOCR1 is an 8-bit readable/writable register that enables/disables PWM synchronized toggle

output in complementary PWM mode/reset synchronized PWM mode, and controls output level

inversion of PWM output.

Bit:

Initial value:

R/W:

7654321

00000000

R/W

R/(W)*1 R/W

R/W

Note: 1. This bit can be set to 1 only once after a power-on reset. After 1 is written, 0 cannot be written to the bit.

—

PSYE

—

TOCL TOCS OLSN OLSP

Bit

Bit Name

Initial

value

R/W

Description

—

Reserved

This bit is always read as 0. The write value should

always be 0.

PSYE

R/W

PWM Synchronous Output Enable

This bit selects the enable/disable of toggle output

synchronized with the PWM period.

0: Toggle output is disabled

1: Toggle output is enabled

5, 4

—

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

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