SH7261 datasheet(570/1348 Pages) RENESAS

570 / 1348 page

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 Sep. 07, 2007 Page 538 of 1312

REJ09B0320-0200

Channel

Name

Interrupt Source

Interrupt Flag

DMAC

Activation

Priority

TGIA_3

TGRA_3 input capture/compare match

TGFA_3

Possible

High

TGIB_3

TGRB_3 input capture/compare match

TGFB_3

Not possible

TGIC_3

TGRC_3 input capture/compare match

TGFC_3

Not possible

TGID_3

TGRD_3 input capture/compare match

TGFD_3

Not possible

TCIV_3

TCNT_3 overflow

TCFV_3

Not possible

TGIA_4

TGRA_4 input capture/compare match

TGFA_4

Possible

TGIB_4

TGRB_4 input capture/compare match

TGFB_4

Not possible

TGIC_4

TGRC_4 input capture/compare match

TGFC_4

Not possible

TGID_4

TGRD_4 input capture/compare match

TGFD_4

Not possible

TCIV_4

TCNT_4 overflow/underflow

TCFV_4

Not possible

TGIU_5

TGRU_5 input capture/compare match

TGFU_5

Not possible

TGIV_5

TGRV_5 input capture/compare match

TGFV_5

Not possible

TGIW_5

TGRW_5 input capture/compare match

TGFW_5

Not possible

Low

Note:

This table shows the initial state immediately after a reset. The relative channel priorities

can be changed by the interrupt controller.

(1)

Input Capture/Compare Match Interrupt

An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1

by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt

request is cleared by clearing the TGF flag to 0. The MTU2 has 21 input capture/compare match

interrupts, six for channel 0, four each for channels 3 and 4, two each for channels 1 and 2, and

three for channel 5. The TGFE_0 and TGFF_0 flags in channel 0 are not set by the occurrence of

an input capture.

(2)

Overflow Interrupt

An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to

1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing

the TCFV flag to 0. The MTU2 has five overflow interrupts, one for each channel.

(3)

Underflow Interrupt

An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to

1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing

the TCFU flag to 0. The MTU2 has two underflow interrupts, one each for channels 1 and 2.

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