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SH7261 Datasheet(PDF) 567 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 567 Page - Renesas Technology Corp

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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Rev. 2.00 Sep. 07, 2007 Page 535 of 1312
REJ09B0320-0200
(1)
Example of Dead Time Compensation Setting Procedure
Figure 12.80 shows an example of dead time compensation setting procedure by using three
counters in channel 5.
TCNT_5 input capture occurs
External pulse width
measurement
Complementary PWM mode
Interrupt processing
Notes:
The PFC settings must be completed in advance.
* As an interrupt flag is set under the capture condition specified in TIOR, do not enable
interrupt requests in TIER_5.
Start count operation in
channels 3 to 5
[3]
[4] *
[5]
[1]
[2]
[1] Place channels 3 and 4 in complementary PWM mode. For details,
refer to section 12.4.8, Complementary PWM Mode.
[2] Specify the external pulse width measurement function for the target
TIOR in channel 5. For details, refer to section 12.4.10, External
Pulse Width Measurement.
[3] Set bits CST3 and CST4 in TSTR and bits CST5U, CST5V, and
CST5W in TSTR2 to 1 to start count operation.
[4] When the capture condition specified in TIOR is satisfied, the
TCNT_5 value is captured in TGR_5.
[5] For U-phase dead time compensation, when an interrupt is
generated at the crest (TGIA_3) or trough (TCIV_4) in
complementary PWM mode, read the TGRU_5 value, calculate the
difference in time in TGRB_3, and write the corrected value to
TGRD_3 in the interrupt processing.
For the V phase and W phase, read the TGRV_5 and TGRW_5
values and write the corrected values to TGRC_4 and TGRD_4,
respectively, in the same way as for U-phase compensation.
The TCNT_5 value should be cleared through the TCNTCMPCLR
setting or by software.
Figure 12.80 Example of Dead Time Compensation Setting Procedure
MTU
ch3/4
ch5
Complementary
PWM output
Dead time
delay input
Inverter output
monitor signals
-+
U
V
W
U
V
W
U
V
W
Motor
≠
DC
Figure 12.81 Example of Motor Control Circuit Configuration



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