SH7261 datasheet(682/1348 Pages) RENESAS

682 / 1348 page

Section 15 Realtime Clock (RTC)

Rev. 2.00 Sep. 07, 2007 Page 650 of 1312

REJ09B0320-0200

15.3.9

Second Alarm Register (RSECAR)

RSECAR is an alarm register corresponding to the BCD coded second counter RSECCNT of the

RTC. When the ENB bit is set to 1, a comparison with the RSECCNT value is performed. From

among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and

alarm register comparison is performed only on those with ENB bits set to 1, and if each of those

coincides, an alarm flag of RCR1 is set to 1.

The assignable range is from 00 through 59

+ ENB bits (practically in BCD), otherwise operation

errors occur.

The ENB bit in RSECAR is initialized to 0 by a power-on reset or in deep standby mode. The

other bits are not initialized by a power-on reset or manual reset, or in deep standby and software

standby modes.

R/W

Bit:

Initial value:

R/W:

ENB

———————

10 seconds

1 second

Bit

Bit Name

Initial

Value

R/W

Description

ENB

R/W

When this bit is set to 1, a comparison with the

RSECCNT value is performed.

6 to 4

10 seconds

Undefined

R/W

Ten's position of seconds setting value

3 to 0

1 second

Undefined

R/W

One's position of seconds setting value

SH7261 Datasheet(PDF) 682 Page - Renesas Technology Corp

SH7261 Datasheet(HTML) 682 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL