SH7261 datasheet(742/1348 Pages) RENESAS

742 / 1348 page

Section 16 Serial Communication Interface with FIFO (SCIF)

Rev. 2.00 Sep. 07, 2007 Page 710 of 1312

REJ09B0320-0200

(2)

Clock

An internal clock generated by the on-chip baud rate generator or an external clock input from the

SCK pin can be selected as the SCIF transmit/receive clock. The clock source is selected by the

A bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control

When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the

desired bit rate.

When the SCIF operates on an internal clock, it can output a clock signal on the SCK pin. The

frequency of this output clock is 16 times the desired bit rate.

(3)

Transmitting and Receiving Data

• SCIF Initialization (Asynchronous Mode)

Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register

(SCSCR), then initialize the SCIF as follows.

When changing the operation mode or the communication format, always clear the TE and RE bits

to 0 before following the procedure given below. Clearing TE to 0 initializes the transmit shift

(SCFSR), transmit FIFO data register (SCFTDR), or receive FIFO data register (SCFRDR), which

retain their previous contents. Clear TE to 0 after all transmit data has been transmitted and the

TEND flag in the SCFSR is set. The TE bit can be cleared to 0 during transmission, but the

transmit data goes to the Mark state after the bit is cleared to 0. Set the TFRST bit in SCFCR to 1

and reset SCFTDR before TE is set again to start transmission.

When an external clock is used, the clock should not be stopped during initialization or subsequent

operation. SCIF operation becomes unreliable if the clock is stopped.

SH7261 Datasheet(PDF) 742 Page - Renesas Technology Corp