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SH7261 Datasheet(PDF) 745 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 745 Page - Renesas Technology Corp

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Section 16 Serial Communication Interface with FIFO (SCIF)
Rev. 2.00 Sep. 07, 2007 Page 713 of 1312
REJ09B0320-0200
In serial transmission, the SCIF operates as described below.
1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the
data from SCFTDR to the transmit shift register (SCTSR) and starts transmitting. Confirm that
the TDFE flag in the serial status register (SCFSR) is set to 1 before writing transmit data to
SCFTDR. The number of data bytes that can be written is (16 – transmit trigger setting).
2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive
transmit operations are performed until there is no transmit data left in SCFTDR. When the
number of transmit data bytes in SCFTDR falls below the transmit trigger number set in the
FIFO control register (SCFCR), the TDFE flag is set. If the TIE bit in the serial control register
(SCSR) is set to 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) request is
generated.
The serial transmit data is sent from the TxD pin in the following order.
A. Start bit: One-bit 0 is output.
B. Transmit data: 8-bit or 7-bit data is output in LSB-first order.
C. Parity bit: One parity bit (even or odd parity) is output. (A format in which a parity bit is
not output can also be selected.)
D. Stop bit(s): One or two 1 bits (stop bits) are output.
E. Mark state: 1 is output continuously until the start bit that starts the next transmission is
sent.
3. The SCIF checks the SCFTDR transmit data at the timing for sending the stop bit. If data is
present, the data is transferred from SCFTDR to SCTSR, the stop bit is sent, and then serial
transmission of the next frame is started.
Figure 16.5 shows an example of the operation for transmission.
TDFE
0
0/1
1
1
1
D0
D1
D7
0
0/1
1
D0
D1
D7
TEND
Serial
data
Start
bit
Data
Parity
bit
Stop
bit
Start
bit
Idle state
(mark state)
Data
Parity
bit
Stop
bit
TXI interrupt
request
Data written to SCFTDR and TDFE
flag read as 1 then cleared to 0 by
TXI interrupt handler
One frame
TXI interrupt
request
Figure 16.5 Example of Transmit Operation (8-Bit Data, Parity, 1 Stop Bit)



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