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SH7261 Datasheet(PDF) 749 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 749 Page - Renesas Technology Corp

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Section 16 Serial Communication Interface with FIFO (SCIF)
Rev. 2.00 Sep. 07, 2007 Page 717 of 1312
REJ09B0320-0200
16.4.3
Operation in Clocked Synchronous Mode
In clocked synchronous mode, the SCIF transmits and receives data in synchronization with clock
pulses. This mode is suitable for high-speed serial communication.
The SCIF transmitter and receiver are independent, so full-duplex communication is possible
while sharing the same clock. The transmitter and receiver are also 16-byte FIFO buffered, so
continuous transmitting or receiving is possible by reading or writing data while transmitting or
receiving is in progress.
Figure 16.9 shows the general format in clocked synchronous serial communication.
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
*
*
LSB
MSB
Don't care
Don't care
One unit of transfer data (character or frame)
Serial data
Serial clock
Note: * High except in continuous transfer
Figure 16.9 Data Format in Clocked Synchronous Communication
In clocked synchronous serial communication, each data bit is output on the communication line
from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of
the serial clock.
In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB
(last). After output of the MSB, the communication line remains in the state of the MSB.
In clocked synchronous mode, the SCIF receives data by synchronizing with the rising edge of the
serial clock.



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