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SH7261 Datasheet(PDF) 747 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 747 Page - Renesas Technology Corp |
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747 / 1348 page  Section 16 Serial Communication Interface with FIFO (SCIF) Rev. 2.00 Sep. 07, 2007 Page 715 of 1312 REJ09B0320-0200 Error handling Receive error handling ER = 1? BRK = 1? Break handling DR = 1? Read receive data in SCFRDR Clear DR, ER, BRK flags in SCFSR, and ORER flag in SCLSR, to 0 End Yes Yes Yes No Overrun error handling ORER = 1? Yes No No No • Whether a framing error or parity error has occurred in the receive data that is to be read from the receive FIFO data register (SCFRDR) can be ascertained from the FER and PER bits in the serial status register (SCFSR). • When a break signal is received, receive data is not transferred to SCFRDR while the BRK flag is set. However, note that the last data in SCFRDR is H'00, and the break data in which a framing error occurred is stored. Figure 16.7 Sample Flowchart for Receiving Serial Data (cont) |
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