SH7261 datasheet(751/1348 Pages) RENESAS

751 / 1348 page

Section 16 Serial Communication Interface with FIFO (SCIF)

Rev. 2.00 Sep. 07, 2007 Page 719 of 1312

REJ09B0320-0200

Figure 16.10 shows a sample flowchart for initializing the SCIF.

Start of initialization

Clear TE and RE bits

in SCSCR to 0

Set TFRST and RFRST bits

in SCFCR to 1 to clear

the FIFO buffer

After reading ER, DR,

and BRK flags in SCFSR,

write 0 to clear them

Set CKE[1:0] bits

in SCSCR (leaving TE, RE, TIE,

and RIE bits cleared to 0)

Set data transfer format

in SCSMR

Set value in SCBRR

Set RTRG[1:0] and TTRG[1:0] bits

in SCFCR, and clear TFRST

and RFRST bits to 0

Set TE and RE bits in SCSCR to 1,

and set TIE, RIE, and REIE bits

End of initialization

Leave the TE and RE bits cleared

to 0 until the initialization almost

ends.

Set the data transfer format in

SCSMR.

Set the CKE1 and CKE0 bits.

Write a value corresponding to

the bit rate into SCBRR. This

is not necessary if an external

clock is used.

Sets PFC for external pins used.

Set as RxD input at reciving and

TxD at transmission.

Set the TE or RE bit in SCSCR

to 1. Also set the TIE, RIE, and

REIE bits to enable the TxD,

RxD, and SCK pins to be used.

When transmitting, the TxD pin

will go to the mark state.

When receiving in clocked

synchronous mode with the

synchronization clock output (clock

master) selected, a clock starts to

be output from the SCK pin at this

point.

[1]

[2]

[3]

[4]

[5]

[6]

[2]

[3]

[4]

[6]

PFC setting for external pins used

SCK, TxD, RxD

[5]

Figure 16.10 Sample Flowchart for SCIF Initialization

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