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SH7261 Datasheet(PDF) 746 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 746 Page - Renesas Technology Corp

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Section 16 Serial Communication Interface with FIFO (SCIF)
Rev. 2.00 Sep. 07, 2007 Page 714 of 1312
REJ09B0320-0200
• Receiving Serial Data (Asynchronous Mode)
Figures 16.6 and 16.7 show sample flowcharts for serial reception.
Use the following procedure for serial data reception after enabling the SCIF for reception.
Start of reception
Read ER, DR, BRK flags in
SCFSR and ORER
flag in SCLSR
ER, DR, BRK or ORER = 1?
Read RDF flag in SCFSR
RDF = 1?
Read receive data in
SCFRDR, and clear RDF
flag in SCFSR to 0
All data received?
Clear RE bit in SCSCR to 0
End of reception
Yes
No
Yes
Yes
No
No
Error handling
[1] Receive error handling and break detection:
Read the DR, ER, and BRK flags in SCFSR, and the
ORER flag in SCLSR, to identify any error, perform the
appropriate error handling, then clear the DR, ER,
BRK, and ORER flags to 0. In the case of a framing
error, a break can also be detected by reading the
value of the RxD pin.
[2] SCIF status check and receive data read:
Read SCFSR and check that RDF = 1, then read the
receive data in SCFRDR, read 1 from the RDF flag,
and then clear the RDF flag to 0. The transition of the
RDF flag from 0 to 1 can also be identified by an RXI
interrupt.
[3] Serial reception continuation procedure:
To continue serial reception, read at least the receive
trigger set number of receive data bytes from
SCFRDR, read 1 from the RDF flag, then clear the
RDF flag to 0. The number of receive data bytes in
SCFRDR can be ascertained by reading from
SCRFDR.
[1]
[2]
[3]
Figure 16.6 Sample Flowchart for Receiving Serial Data



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