SH7261 datasheet(883/1348 Pages) RENESAS

883 / 1348 page

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]

Rev. 2.00 Sep. 07, 2007 Page 851 of 1312

REJ09B0320-0200

19.5.4

Abort Acknowledge Register 0 (ABACK0)

The ABACK0 is a 16-bit read/conditionally-write registers. This register is used to signal to the

CPU that a mailbox transmission has been aborted as per its request. When an abort has succeeded

the RCAN-ET sets the corresponding bit in the ABACK register. The CPU may clear the Abort

Acknowledge bit by writing a '1' to the corresponding bit location. Writing a '0' has no effect. An

ABACK bit position is set by the RCAN-ET to acknowledge that a TXPR bit has been cleared by

the corresponding TXCR bit.

• ABACK0

Bit:

Initial value:

R/W:

—

000000000000000

R/W*

ABACK0[15:1]

Note: * Only when writing a '1' to clear.

Bit 15 to 1 — Notifies that the requested transmission cancellation of the corresponding Mailbox

has been performed successfully. The bit 15 to 1 corresponds to Mailbox-15 to 1 respectively.

Bit[15:1]:ABACK0

Description

[Clearing Condition] Writing '1' (Initial value)

Corresponding Mailbox has cancelled transmission of message (Data or

Remote Frame)

[Setting Condition] Completion of transmission cancellation for corresponding

mailbox

Bit 0 — This bit is always '0' as this is a receive-only mailbox. Writing a '1' to this bit position has

no effect and always read back as a '0'.

SH7261 Datasheet(PDF) 883 Page - Renesas Technology Corp