SH7261 datasheet(885/1348 Pages) RENESAS

885 / 1348 page

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]

Rev. 2.00 Sep. 07, 2007 Page 853 of 1312

REJ09B0320-0200

19.5.6

Remote Frame Receive Pending Register 0 (RFPR0)

The RFPR0 is a 16-bit read/conditionally-write registers. The RFPR is a register that contains the

received Remote Frame pending flags associated with the configured Receive Mailboxes. When a

CAN Remote Frame is successfully stored in a receive mailbox the corresponding bit is set in the

RFPR. The bit may be cleared by writing a '1' to the corresponding bit position. Writing a '0' has

no effect. In effect there is a bit position for all mailboxes. However, the bit may only be set if the

mailbox is configured by its MBC (Mailbox Configuration) to receive Remote Frames. When a

RFPR bit is set, it also sets IRR2 (Remote Frame Request Interrupt Flag) if its MBIMR (Mailbox

Interrupt Mask Register) is not set, and the interrupt signal is generated if IMR2 is not set. Please

note that these bits are only set by receiving Remote Frames and not by receiving Data frames.

• RFPR0

Bit:

Initial value:

R/W:

0000000000000000

R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*

RFPR0[15:0]

Note: * Only when writing a '1' to clear.

Bit 15 to 0 — Remote Request pending flags for mailboxes 15 to 0 respectively.

Bit[15:0]: RFPR0

Description

[Clearing Condition] Writing '1' (Initial value)

Corresponding Mailbox received Remote Frame

[Setting Condition] Completion of remote frame receive in corresponding

mailbox

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