SH7261 datasheet(889/1348 Pages) RENESAS

889 / 1348 page

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]

Rev. 2.00 Sep. 07, 2007 Page 857 of 1312

REJ09B0320-0200

Power On/SW Reset*1

clear IRR[0] Bit

GSR[3] = 0?

Detect 11 recessive bits and

Join the CAN bus activity

RCAN-ET is in Tx_Rx Mode

Set TXPR to start transmission

or stay idle to receive

Configure MCR[15]

Clear MCR[0]

Clear Required IMR Bits

Set Bit Timing (BCR)

Mailbox Setting

(STD-ID, EXT-ID, LAFM, DLC,

RTR, IDE, MBC, MBIMR, DART,

ATX, NMC, Message-Data)*2

IRR[0] = 1, GSR[3] = 1 (automatically)

No*3

Yes

Transmission_Reception

(Tx_Rx) Mode

Receive*4

Transmit*4

Notes: 1. SW reset could be performed at any time by setting MCR[0] = 1.

2. Mailboxes are comprised of RAMs, therefore, please initialize all the mailboxes enabled by MBC.

3. It takes approximately 25 peripheral bus cycles for GSR[3] to be cleared to 0.

4. If there is no TXPR set, RCAN-ET will receive the next incoming message.

If there is a TXPR(s) set, RCAN-ET will start transmission of the message and will be arbitrated by the CAN bus.

If it loses the arbitration, it will become a receiver.

MCR[0] = 1

(automatically in hardware reset only)

Configuration Mode

Figure 19.6 Reset Sequence

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