SH7261 datasheet(886/1348 Pages) RENESAS

886 / 1348 page

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]

Rev. 2.00 Sep. 07, 2007 Page 854 of 1312

REJ09B0320-0200

19.5.7

Mailbox Interrupt Mask Register 0 (MBIMR0)

The MBIMR1 and MBIMR0 are 16-bit read/write registers. The MBIMR only prevents the setting

of IRR related to the Mailbox activities, that are IRR[1] – Data Frame Received Interrupt, IRR[2]

– Remote Frame Request Interrupt, IRR[8] – Mailbox Empty Interrupt, and IRR[9] – Message

OverRun/OverWrite Interrupt. If a mailbox is configured as receive, a mask at the corresponding

bit position prevents the generation of a receive interrupt (IRR[1] and IRR[2] and IRR[9]) but

does not prevent the setting of the corresponding bit in the RXPR or RFPR or UMSR. Similarly

when a mailbox has been configured for transmission, a mask prevents the generation of an

Interrupt signal and setting of an Mailbox Empty Interrupt due to successful transmission or

abortion of transmission (IRR[8]), however, it does not prevent the RCAN-ET from clearing the

corresponding TXPR/TXCR bit + setting the TXACK bit for successful transmission, and it does

not prevent the RCAN-ET from clearing the corresponding TXPR/TXCR bit + setting the

ABACK bit for abortion of the transmission.

A mask is set by writing a '1' to the corresponding bit position for the mailbox activity to be

masked. At reset all mailbox interrupts are masked.

• MBIMR0

Bit:

Initial value:

R/W:

1111111111111111

R/W

MBIMR0[15:0]

Bit 15 to 0 — Enable or disable interrupt requests from individual Mailbox-15 to Mailbox-0

respectively.

Bit[15:0]: MBIMR0 Description

Interrupt Request from IRR1/IRR2/IRR8/IRR9 enabled

Interrupt Request from IRR1/IRR2/IRR8/IRR9 disabled (initial value)

SH7261 Datasheet(PDF) 886 Page - Renesas Technology Corp