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SH7261 Datasheet(PDF) 1000 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 1000 Page - Renesas Technology Corp

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Section 21 CD-ROM Decoder (ROM-DEC)
Rev. 2.00 Sep. 07, 2007 Page 968 of 1312
REJ09B0320-0200
21.3.16
Buffer Overflow Status Register (CBUFST2)
CBUFST2 indicates that a sector-to-sector transition occurred before data transfer to the buffer is
completed.
76543210
Bit:
Initial value:
R/W:
00000000
RRRRRRRR
BUF_
NG
—————
—
—
Bit
Bit Name
Initial
Value
R/W
Description
7
BUF_NG
0
R
Indicates that a sector-to-sector transition has occurred
before the data transfer to the buffer is completed. This
bit is set to 1 when the data of a third sector are input
while data for the output stream from the CD-ROM
decoder remains unread. No interrupt is generated.
Once this bit has been set, its value will not recover
unless it is reset by the LOGICRST bit in the
ROMDECRST register.
6 to 0
All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
21.3.17
Pre-ECC Correction Header: Minutes Data Register (HEAD00)
HEAD00 indicates the minutes value in the header before ECC correction.
76543210
Bit:
Initial value:
R/W:
00000000
RRRRRRRR
HEAD00[7:0]
Bit
Bit Name
Initial
Value
R/W
Description
7 to 0
HEAD00[7:0]
All 0
R
Minutes value in the header before ECC correction



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