SH7261 datasheet(1048/1348 Pages) RENESAS

1048 / 1348 page

Section 22 A/D Converter (ADC)

Rev. 2.00 Sep. 07, 2007 Page 1016 of 1312

REJ09B0320-0200

22.3.2

A/D Control/Status Register (ADCSR)

ADCSR is a 16-bit readable/writable register that selects the mode, controls the A/D converter,

and enables or disables starting of A/D conversion by external trigger input.

ADCSR is initialized to H'0040 by a power-on reset as well as in deep standby mode, software

standby mode or module standby mode.

987654321

0000000001000000

R/(W)* R/W

R/W

Bit:

Initial value:

R/W:

Note:

Only 0 can be written to clear the flag after 1 is read.

ADF

ADIE ADST

—

TRGS[3:0]

CKS[1:0]

MDS[2:0]

CH[2:0]

Bit

Bit Name

Initial

Value

R/W

Description

ADF

R/(W)*

A/D End Flag

Status flag indicating the end of A/D conversion.

[Clearing conditions]

• Cleared by reading ADF while ADF = 1, then

writing 0 to ADF

• Cleared when DMAC is activated by ADI interrupt

and ADDR is read

[Setting conditions]

• A/D conversion ends in single mode

• A/D conversion ends for the selected channels in

multi mode

• A/D conversion ends for the selected channels in

scan mode

ADIE

R/W

A/D Interrupt Enable

Enables or disables the interrupt (ADI) requested at

the end of A/D conversion. Set the ADIE bit while A/D

conversion is not being made.

0: A/D end interrupt request (ADI) is disabled

1: A/D end interrupt request (ADI) is enabled

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