SH7672 datasheet(396/1292 Pages) RENESAS

396 / 1292 page

Section 10 Watchdog Timer (WDT)

Rev. 1.00 Nov. 14, 2007 Page 370 of 1262

REJ09B0437-0100

5. The counter stops at the value of H'00.

6. Before changing WTCNT after execution of the frequency change instruction, always confirm

that the value of WTCNT is H'00 by reading from WTCNT.

10.4.3

Using Watchdog Timer Mode

1. Set the WT/

IT bit in WTCSR to 1 to set the type of count clock in the CKS2 to CKS0 bits,

whether this LSI is to be reset internally or not in the RSTE bit in WRCSR, and the initial

value of the counter in WTCNT.

2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode.

3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent

the counter from overflowing.

4. When the counter overflows, the WDT sets the WOVF flag in WRCSR to 1, and the

WDTOVF signal is output externally (figure 10.4). The WDTOVF signal can be used to reset

the system. The

WDTOVF signal is output for 64 × Pφ clock cycles.

5. If the RSTE bit in WRCSR is set to 1, a signal to reset the inside of this LSI can be generated

simultaneously with the

WDTOVF signal. The internal reset signal is output for 128 × Pφ

clock cycles.

6. When a WDT overflow reset is generated simultaneously with a reset input on the

RES pin,

the

RES pin reset takes priority, and the WOVF bit in WRCSR is cleared to 0.

SH7672 Datasheet(PDF) 396 Page - Renesas Technology Corp