SH7672 datasheet(423/1292 Pages) RENESAS

423 / 1292 page

Section 12 Ethernet Controller (EtherC)

Rev. 1.00 Nov. 14, 2007 Page 397 of 1262

REJ09B0437-0100

12.2

Input/Output Pins

Table 12.1 lists the pin configuration of the EtherC.

Table 12.1

Pin Configuration

Port

Abbreviation I/O

Function

TX-CLK*

Input

Transmit Clock

Timing reference signal for the TX-EN, MII_TXD3 to MII_TXD0,

TX-ER signals

RX-CLK*

Input

Receive Clock

Timing reference signal for the RX-DV, MII_RXD3 to MII_RXD0,

RX-ER signals

TX-EN*

Output

Transmit Enable

Indicates that transmit data is ready on pins MII_TXD3 to

MII_TXD0.

MII_TXD3 to

MII_TXD0*

Output

Transmit Data

4-bit transmit data

TX-ER*

Output

Transmit Error

Notifies the PHY-LSI of error during transmission

RX-DV*

Input

Receive Data Valid

Indicates that valid receive data is on pins MII_RXD3 to

MII_RXD0.

MII_RXD3 to

MII_RXD0*

Input

Receive Data

4-bit receive data

RX-ER*

Input

Receive Error

Identifies error state occurred during data reception.

CRS

Input

Carrier Detection

Carrier detection signal

COL

Input

Collision Detection

Collision detection signal

MDC

Output

Management Data Clock

Reference clock signal for information transfer via MDIO

MDIO

Input/

Output

Management Data I/O

Bidirectional signal for exchange of management information

between this LSI and PHY

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