SH7672 datasheet(447/1292 Pages) RENESAS

Part #	SH7672

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

PDF	1292 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 12 Ethernet Controller (EtherC)

Rev. 1.00 Nov. 14, 2007 Page 421 of 1262

REJ09B0437-0100

12.3.19

IPG Register (IPGR)

IPGR sets the IPG (Inter Packet Gap). This register must not be changed while the transmitting

and receiving functions of the EtherC mode register (ECMR) are enabled. (For details, refer to

section 12.4.6, Operation by IPG Setting.)

Bit:

Initial value:

R/W:

9876543210

Bit:

Initial value:

R/W:

0000000000000000

RRRRRRRRRRRRRRRR

0000000000010100

RRRRRRRRRRR

R/W

----------------

-----------

IPG[4:0]

Bit

Bit Name

Initial

Value

R/W

Description

31 to 5



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

4 to 0

IPG[4:0]

H'13

R/W

Inter Packet Gap

Sets the IPG value every 4-bit time.

H'00: 20-bit time

H'01: 24-bit time

H'13: 96-bit time (Initial value)

H'1F: 144-bit time

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