SH7672 datasheet(509/1292 Pages) RENESAS

509 / 1292 page

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev. 1.00 Nov. 14, 2007 Page 483 of 1262

REJ09B0437-0100

13.3.3

Reception

When the receive function is enabled and the CPU sets the receive request bit (RR) in the E-

DMAC receive request register (EDRRR), the E-DMAC reads the descriptor following the

previously used one from the receive descriptor list (the descriptor indicated by the receive

descriptor list's starting address register (RDLA) is used at the initial state), and then enters the

receive-standby state. If the setting of the RACT bit is "active" and an own-address frame is

received, the E-DMAC transfers the frame to the receive buffer specified by RD2. If the data

length of the received frame is greater than the buffer length given by RD1, the E-DMAC

performs write-back to the descriptor when the buffer is full (RFP = 10 or 00), then reads the next

descriptor. The E-DMAC then continues to transfer data to the receive buffer specified by the new

RD2. When frame reception is completed, or if frame reception is suspended because of a certain

kind of error, the E-DMAC performs write-back to the relevant descriptor (RFP = 11 or 01), and

then ends the receive processing. The E-DMAC then reads the next descriptor and enters the

receive-standby state again.

To receive frames continuously, the receive enable control bit (RNC) must be set to 1 in the

receive control register (RCR). After initialization, this bit is cleared to 0.

SH7672 Datasheet(PDF) 509 Page - Renesas Technology Corp