SH7672 datasheet(526/1292 Pages) RENESAS

526 / 1292 page

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)

Rev. 1.00 Nov. 14, 2007 Page 500 of 1262

REJ09B0437-0100

Bit

Bit Name

Initial

Value

R/W

Description

C[i]C_VLD

R/W

Variable-Length Descriptor Control Flag

0: Fixed-length descriptor (32 bytes)

1: Variable-length descriptor (16/32 bytes)

The A-DMAC channel uses the 32-byte fixed length

structure or 16/32-byte variable-length structure. If

this bit is set to 0 to define the descriptor as the

fixed-length, the descriptor is always read as 32

bytes. If this bit is set to 1 to define the descriptor as

the variable-length, the first 16 bytes are read, and if

r_cid4/r_cid5/r_cid6/r_cid7 information is required,

the remaining 16 bytes are read according to the

contents of r_cidm/r_cihm.

7 to 5

—

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

C[i]C_EIE

R/W

"Processing End" Interrupt Request Enable

When processing ends, specifies whether to enable

or disable the "processing end" interrupt request.

0: Disables the "processing end" interrupt request.

1: Enables the "processing end" interrupt request.

A-DMAC channel [i] processing end means fetching

of depleted descriptors (invalid descriptors

(descriptors where C[i]F0 is set to 0)).

3 to 1

—

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

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