SH7672 datasheet(522/1292 Pages) RENESAS

Part #	SH7672

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

PDF	1292 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)

Rev. 1.00 Nov. 14, 2007 Page 496 of 1262

REJ09B0437-0100

Table 14.1

A-DMAC Submodules

Submodule Name

Function

Channel for checksum

processing

• DMA automatic processing based on descriptors

• Checksum operation

• Continuous execution of checksum

FEC channel

• DMA automatic processing based on descriptors

• XOR operation for any number of data items

Arbiter

• Arbitrates requests from the channel for checksum processing

and FEC channel.

• Channel arbitration mode is round robin scheduling.

I-BUS interface

• Conversion between I-BUS protocol and A-DMAC protocol

• Distribution of register R/W requests from the CPU to each

module

STIF interface

• Conversion between STIF protocol and A-DMAC protocol

• STIF0 is fixed at channel 0 for encryption/authentication.

• STIF1 is fixed at channel 1 for encryption/authentication.

SH7672 Datasheet(PDF) 522 Page - Renesas Technology Corp