SH7672 datasheet(520/1292 Pages) RENESAS

520 / 1292 page

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)

Rev. 1.00 Nov. 14, 2007 Page 494 of 1262

REJ09B0437-0100

14.1.2

Overall Configuration of the A-DMAC

The A-DMAC is configured as shown in figure 14.1. Table 14.2 gives an overview of A-DMAC

submodules.

The A-DMAC is connected to the I-BUS via the I-BUS interface, to the STIF0 via the STIF0

interface, and to the STIF1 via the STIF1 interface. The I-BUS is a shared bus in this LSI

operating on the B clock. The STIF is an I/O port for MPEG-2 TS/PS format data. The STIF0 is

fixed at CH0 and the STIF1 fixed at CH1.

The A-DMAC has two channels for checksum operation that operate on descriptors. Aside from

these channels, the A-DMAC has an FEC channel dedicated for FEC operation. This FEC channel

performs XOR operation of FEC operation.

These modules operate in parallel. For example, when the bus for channel 0 for checksum

processing is accessed, channel 1 for checksum processing can perform checksum operation.

The arbiter is a module that arbitrates the requests sent from each checksum processing channel

and each initiator of the FEC channel. The arbiter arbitrates requests from an initiator in round

robin scheduling. If you want to execute CH0 and CH1 simultaneously and raise the priority of

CH0 or CH1, the arbiter controls the priorities in descriptor ring units (example: When the

descriptor of CH0 or CH1, whichever has a lower priority, runs dry, the arbiter piles up the next

descriptor after a certain idling) or controls the priorities by suspending channel processing of

lower priority.

SH7672 Datasheet(PDF) 520 Page - Renesas Technology Corp