SH7672 datasheet(105/1292 Pages) RENESAS

105 / 1292 page

Section 3

Floating-Point Unit (FPU)

Rev. 1.00

Nov. 14, 2007

Page 79 of 1262

REJ09B0437-0100

3.2.2

Non-Numbers (NaN)

Figure 3.3 shows the bit pattern of a non-number (NaN). A value is NaN in the following case:

• Sign bit: Don't care

• Exponent field: All bits are 1

• Fraction field: At least one bit is 1

The NaN is a signaling NaN (sNaN) if the MSB of the fraction field is 1, and a quiet NaN (qNaN)

if the MSB is 0.

N = 1: sNaN

N = 0: qNaN

11111111

Nxxxxxxxxxxxxxxxxxxxxxx

Figure 3.3

Single-Precision NaN Bit Pattern

An sNaN is input in an operation, except copy, FABS, and FNEG, that generates a floating-point

value.

• When the EN.V bit in FPSCR is 0, the operation result (output) is a qNaN.

• When the EN.V bit in FPSCR is 1, an invalid operation exception will be generated. In this

case, the contents of the operation destination register are unchanged.

If a qNaN is input in an operation that generates a floating-point value, and an sNaN has not been

input in that operation, the output will always be a qNaN irrespective of the setting of the EN.V bit

in FPSCR. An exception will not be generated in this case.

The qNAN values as operation results are as follows:

• Single-precision qNaN: H'7FBF FFFF

• Double-precision qNaN: H'7FF7 FFFF FFFF FFFF

See the individual instruction descriptions for details of floating-point operations when a non-

number (NaN) is input.

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