SH7672 datasheet(124/1292 Pages) RENESAS

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Section 4 Cache

Rev. 1.00 Nov. 14, 2007 Page 98 of 1262

REJ09B0437-0100

4.3.2

Read Access

(1)

Read Hit

In a read access, data is transferred from the cache to the CPU. LRU is updated so that the hit way

is the latest.

(2)

Read Miss

An external bus cycle starts and the entry is updated. The way replaced follows table 4.4. Entries

are updated in 16-byte units. When the desired data that caused the miss is loaded from external

memory to the cache, the data is transferred to the CPU in parallel with being loaded to the cache.

When it is loaded in the cache, the V bit is set to 1, and LRU is updated so that the replaced way

becomes the latest. In operand cache, the U bit is additionally cleared to 0. When the U bit of the

entry to be replaced by updating the entry in write-back mode is 1, the cache update cycle starts

after the entry is transferred to the write-back buffer. After the cache completes its update cycle,

the write-back buffer writes the entry back to the memory. The write-back unit is 16 bytes.

4.3.3

Prefetch Operation (Only for Operand Cache)

(1)

Prefetch Hit

LRU is updated so that the hit way becomes the latest. The contents in other caches are not

modified. No data is transferred to the CPU.

(2)

Prefetch Miss

No data is transferred to the CPU. The way to be replaced follows table 4.3. Other operations are

the same in case of read miss.

SH7672 Datasheet(PDF) 124 Page - Renesas Technology Corp