SH7672 datasheet(120/1292 Pages) RENESAS

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Section 4 Cache

Rev. 1.00 Nov. 14, 2007 Page 94 of 1262

REJ09B0437-0100

Table 4.3

Way to be Replaced when a Cache Miss Occurs in PREF Instruction

W3LOAD*

W3LOCK

W2LOAD*

W2LOCK

Way to be Replaced

Decided by LRU (table 4.1)

Decided by LRU (table 4.5)

Decided by LRU (table 4.6)

Decided by LRU (table 4.7)

Way 2

Way 3

[Legend]

Don't care

Note:

The W3LOAD and W2LOAD bits should not be set to 1 at the same time.

Table 4.4

Way to be Replaced when a Cache Miss Occurs in Other than PREF Instruction

W3LOAD*

W3LOCK

W2LOAD*

W2LOCK

Way to be Replaced

Decided by LRU (table 4.1)

Decided by LRU (table 4.5)

Decided by LRU (table 4.6)

Decided by LRU (table 4.7)

[Legend]

Don't care

Note:

The W3LOAD and W2LOAD bits should not be set to 1 at the same time.

Table 4.5

LRU and Way Replacement (when W2LOCK=1 and W3LOCK=0)

LRU (Bits 5 to 0)

Way to be Replaced

000000, 000001, 000100, 010100, 100000, 100001, 110000, 110100

000011, 000110, 000111, 001011, 001111, 010110, 011110, 011111

101001, 101011, 111000, 111001, 111011, 111100, 111110, 111111

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