SH7672 datasheet(117/1292 Pages) RENESAS

117 / 1292 page

Section 4 Cache

Rev. 1.00 Nov. 14, 2007 Page 91 of 1262

REJ09B0437-0100

Bit

Bit Name

Initial

Value

R/W

Description

31 to 12



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

ICF

R/W

Instruction Cache Flush

Writing 1 flushes all instruction cache entries (clears the

V and LRU bits of all instruction cache entries to 0).

Always reads 0. Write-back to external memory is not

performed when the instruction cache is flushed.

10, 9



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

ICE

R/W

Instruction Cache Enable

Indicates whether the instruction cache function is

enabled/disabled.

0: Instruction cache disable

1: Instruction cache enable

7 to 4



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

OCF

R/W

Operand Cache Flush

Writing 1 flushes all operand cache entries (clears the

V, U, and LRU bits of all operand cache entries to 0).

Always reads 0. Write-back to external memory is not

performed when the operand cache is flushed.



Reserved

This bit is always read as 0. The write value should

always be 0.

R/W

Write Through

Selects write-back mode or write-through mode.

0: Write-back mode

1: Write-through mode

OCE

R/W

Operand Cache Enable

Indicates whether the operand cache function is

enabled/disabled.

0: Operand cache disable

1: Operand cache enable

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