SH7672 datasheet(114/1292 Pages) RENESAS

114 / 1292 page

Section 4 Cache

Rev. 1.00 Nov. 14, 2007 Page 88 of 1262

REJ09B0437-0100

127

LW0

LW1

LW2

LW3

127

LRU

23 (1 + 1 + 21) bits

128 (32

× 4) bits

6 bits

LW0 to LW3: Longword data 0 to 3

Entry 0

Entry 1

Entry 127

Tag address

Address array (ways 0 to 3)

Data array (ways 0 to 3)

Figure 4.1 Operand Cache Structure

(1)

Address Array

The V bit indicates whether the entry data is valid. When the V bit is 1, data is valid; when 0, data

is not valid.

The U bit (only for operand cache) indicates whether the entry has been written to in write-back

mode. When the U bit is 1, the entry has been written to; when 0, it has not.

The tag address holds the physical address used in the external memory access. It consists of 21

bits (address bits 31 to 11) used for comparison during cache searches. In this LSI, the addresses

of the cache-enabled space are H'00000000 to H'1FFFFFFF (see section 7, Bus State Controller

(BSC)), and therefore the upper three bits of the tag address are cleared to 0.

The V and U bits are initialized to 0 by a power-on reset but not initialized by a manual reset or in

software standby mode. The tag address is not initialized by a power-on reset or manual reset or in

software standby mode.

(2)

Data Array

Holds a 16-byte instruction or data. Entries are registered in the cache in line units (16 bytes).

The data array is not initialized by a power-on reset or manual reset or in software standby mode.

SH7672 Datasheet(PDF) 114 Page - Renesas Technology Corp