SH7672 datasheet(116/1292 Pages) RENESAS

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Section 4 Cache

Rev. 1.00 Nov. 14, 2007 Page 90 of 1262

REJ09B0437-0100

4.2

The cache has the following registers.

Table 4.2

Abbreviation

R/W

Initial Value

Address

Access Size

Cache control register 1

CCR1

R/W

H'00000000

H'FFFC1000

Cache control register 2

CCR2

R/W

H'00000000

H'FFFC1004

4.2.1

Cache Control Register 1 (CCR1)

The instruction cache is enabled or disabled using the ICE bit. The ICF bit controls disabling of all

instruction cache entries. The operand cache is enabled or disabled using the OCE bit. The OCF

bit controls disabling of all operand cache entries. The WT bit selects either write-through mode or

write-back mode for operand cache.

Programs that change the contents of CCR1 should be placed in a cache-disabled space, and a

cache-enabled space should be accessed after reading the contents of CCR1.

CCR1 is initialized to H'00000000 by a power-on reset but not initialized by a manual reset or in

software standby mode.

0000000000000000

RRRRRRRRRRRRRRRR

0000000000000000

R/W

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

----------------

ICF

ICE

OCF

OCE

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