SH7672 datasheet(115/1292 Pages) RENESAS

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Section 4 Cache

Rev. 1.00 Nov. 14, 2007 Page 89 of 1262

REJ09B0437-0100

(3)

LRU

With the 4-way set associative system, up to four instructions or data with the same entry address

can be registered in the cache. When an entry is registered, LRU shows which of the four ways it

is recorded in. There are six LRU bits, controlled by hardware. A least-recently-used (LRU)

algorithm is used to select the way that has been least recently accessed.

Six LRU bits indicate the way to be replaced in case of a cache miss. The relationship between

LRU and way replacement is shown in table 4.1 when the cache lock function (only for operand

cache) is not used (concerning the case where the cache lock function is used, see section 4.2.2,

Cache Control Register 2 (CCR2)). If a bit pattern other than those listed in table 4.1 is set in the

LRU bits by software, the cache will not function correctly. When modifying the LRU bits by

software, set one of the patterns listed in table 4.1.

The LRU bits are initialized to B'000000 by a power-on reset but not initialized by a manual reset

or in software standby mode.

Table 4.1

LRU and Way Replacement (Cache Lock Function Not Used)

LRU (Bits 5 to 0)

Way to be Replaced

000000, 000100, 010100, 100000, 110000, 110100

000001, 000011, 001011, 100001, 101001, 101011

000110, 000111, 001111, 010110, 011110, 011111

111000, 111001, 111011, 111100, 111110, 111111

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