SH7672 datasheet(119/1292 Pages) RENESAS

119 / 1292 page

Section 4 Cache

Rev. 1.00 Nov. 14, 2007 Page 93 of 1262

REJ09B0437-0100

Bit

Bit Name

Initial

Value

R/W

Description

31 to 17



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

R/W

Lock Enable

Controls the cache locking function.

0: Not cache locking mode

1: Cache locking mode

15 to 10



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

W3LOAD*

W3LOCK

R/W

Way 3 Load

Way 3 Lock

When a cache miss occurs by the prefetch instruction

while W3LOAD = 1 and W3LOCK = 1 in cache locking

mode, the data is always loaded into way 3. Under any

other condition, the cache miss data is loaded into the

way to which LRU points.

7 to 2



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

W2LOAD*

W2LOCK

R/W

Way 2 Load

Way 2 Lock

When a cache miss occurs by the prefetch instruction

while W2LOAD = 1 and W2LOCK =1 in cache locking

mode, the data is always loaded into way 2. Under any

other condition, the cache miss data is loaded into the

way to which LRU points.

Note:

The W3LOAD and W2LOAD bits should not be set to 1 at the same time.

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