SH7672 datasheet(118/1292 Pages) RENESAS

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Section 4 Cache

Rev. 1.00 Nov. 14, 2007 Page 92 of 1262

REJ09B0437-0100

4.2.2

Cache Control Register 2 (CCR2)

CCR2 is used to enable or disable the cache locking function for operand cache and is valid in

cache locking mode only. In cache locking mode, the lock enable bit (the LE bit) in CCR2 is set to

1. In non-cache-locking mode, the cache locking function is invalid.

When a cache miss occurs in cache locking mode by executing the prefetch instruction (PREF

@Rn), the line of data pointed to by Rn is loaded into the cache according to bits 9 and 8 (the

W3LOAD and W3LOCK bits) and bits 1 and 0 (the W2LOAD and W2LOCK bits) in CCR2. The

relationship between the setting of each bit and a way, to be replaced when the prefetch instruction

is executed, are listed in table 4.3. On the other hand, when the prefetch instruction is executed

and a cache hit occurs, new data is not fetched and the entry which is already enabled is held. For

example, when the prefetch instruction is executed with W3LOAD = 1 and W3LOCK = 1

specified in cache locking mode while one-line data already exists in way 0 which is specified by

Rn, a cache hit occurs and data is not fetched to way 3.

In the cache access other than the prefetch instruction in cache locking mode, ways to be replaced

by bits W3LOCK and W2LOCK are restricted. The relationship between the setting of each bit in

CCR2 and ways to be replaced are listed in table 4.4.

Programs that change the contents of CCR2 should be placed in a cache-disabled space, and a

cache-enabled space should be accessed after reading the contents of CCR2.

CCR2 is initialized to H'00000000 by a power-on reset but not initialized by a manual reset or in

software standby mode.

0000000000000000

RRRRRRRRRRRRRRR

R/W

0000000000000000

R/W

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

Note:

The W3LOAD and W2LOAD bits should not be set to 1 at the same time.

---------------

------

LOAD*

LOCK

LOAD*

LOCK

------

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