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SH7672 Datasheet(PDF) 166 Page - Renesas Technology Corp |
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SH7672 Datasheet(HTML) 166 Page - Renesas Technology Corp |
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166 / 1292 page ![]() Section 6 Interrupt Controller (INTC) Rev. 1.00 Nov. 14, 2007 Page 140 of 1262 REJ09B0437-0100 Bit Bit Name Initial Value R/W Description 7 IRQ7F 0 R/(W)* 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* IRQ Interrupt Request These bits indicate the status of the IRQ7 to IRQ0 interrupt requests. Level detection: 0: IRQn interrupt request has not occurred [Clearing condition] • IRQn input is high 1: IRQn interrupt has occurred [Setting condition] • IRQn input is low Edge detection: 0: IRQn interrupt request is not detected [Clearing conditions] • Cleared by reading IRQnF while IRQnF = 1, then writing 0 to IRQnF • Cleared by executing IRQn interrupt exception handling 1: IRQn interrupt request is detected [Setting condition] • Edge corresponding to IRQn1S or IRQn0S of ICR1 has occurred at IRQn pin [Legend] n = 7 to 0 |
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