SH7672 datasheet(170/1292 Pages) RENESAS

170 / 1292 page

Section 6 Interrupt Controller (INTC)

Rev. 1.00 Nov. 14, 2007 Page 144 of 1262

REJ09B0437-0100

6.4.4

IRQ Interrupts

IRQ interrupts are input from pins IRQ7 to IRQ0. For the IRQ interrupts, low-level, falling-edge,

rising-edge, or both-edge detection can be selected individually for each pin by the IRQ sense

select bits (IRQ71S to IRQ01S and IRQ70S to IRQ00S) in interrupt control register 1 (ICR1). The

priority level can be set individually in a range from 0 to 15 for each pin by interrupt priority

registers 01 and 02 (IPR01 and IPR02).

When using low-level sensing for IRQ interrupts, an interrupt request signal is sent to the INTC

while the IRQ7 to IRQ0 pins are low. An interrupt request signal is stopped being sent to the

INTC when the IRQ7 to IRQ0 pins are driven high. The status of the interrupt requests can be

checked by reading the IRQ interrupt request bits (IRQ7F to IRQ0F) in the IRQ interrupt request

When using edge-sensing for IRQ interrupts, an interrupt request is detected due to change of the

IRQ7 to IRQ0 pin states, and an interrupt request signal is sent to the INTC. The result of IRQ

interrupt request detection is retained until that interrupt request is accepted. Whether IRQ

interrupt requests have been detected or not can be checked by reading the IRQ7F to IRQ0F bits in

IRQRR. Writing 0 to these bits after reading them as 1 clears the result of IRQ interrupt request

detection.

The IRQ interrupt exception handling sets the I3 to I0 bits in SR to the priority level of the

accepted IRQ interrupt.

When returning from IRQ interrupt exception service routine, execute the RTE instruction after

confirming that the interrupt request has been cleared by the IRQ interrupt request register

(IRQRR) so as not to accidentally receive the interrupt request again.

SH7672 Datasheet(PDF) 170 Page - Renesas Technology Corp