SH7672 datasheet(178/1292 Pages) RENESAS

Part #	SH7672

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

PDF	1292 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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Section 6 Interrupt Controller (INTC)

Rev. 1.00 Nov. 14, 2007 Page 152 of 1262

REJ09B0437-0100

Notes: The interrupt source flag should be cleared in the interrupt handler. After clearing the

interrupt source flag, "time from occurrence of interrupt request until interrupt controller

identifies priority, compares it with mask bits in SR, and sends interrupt request signal to

CPU" shown in table 6.5 is required before the interrupt source sent to the CPU is actually

cancelled. To ensure that an interrupt request that should have been cleared is not

inadvertently accepted again, read the interrupt source flag after it has been cleared, and

then execute an RTE instruction.

* Interrupt requests that are designated as edge-sensing are held pending until the

interrupt requests are accepted. IRQ interrupts, however, can be cancelled by accessing

the IRQ interrupt request register (IRQRR). For details, see section 6.4.4, IRQ

Interrupts.

Interrupts held pending due to edge-sensing are cleared by a power-on reset.

SH7672 Datasheet(PDF) 178 Page - Renesas Technology Corp