38K2 datasheet(114/358 Pages) RENESAS

114 / 358 page

FUNCTIONAL DESCRIPTION

Rev.2.00

Oct 15, 2006

page 95 of 130

38K2 Group

REJ09B0338-0200

HARDWARE

PLL CIRCUIT (FREQUENCY SYNTHESIZER)

The PLL circuit generates fVCO (PLL output clock), which is re-

quired for fUSB (USB clock) and fSYN (fUSB division clock), from

f(XIN) (external input reference clock). Figure 139 shows the PLL

circuit block diagram.

It is possible to input 6 or 12 MHz clock from the externals as a

standard clock input. When using the USB function, set the PLL

operation mode selection bit so that fvco may be set to 48 MHz.

The PLL circuit operates by setting the PLL operation enable bit to

“1”. When supplying fVCO to the USB block, wait for the oscillation

stable time (1ms or less) of PLL before selecting fVCO with the

USB clock selection bit.

According to the setting of the USB clock division ratio selection

bit, the division clock of fUSB is supplied to fSYN. When using this

clock as system clock, set the USB clock division ratio selection

bit so that it may be set to 6 MHz, 8 MHz or 12 MHz. (However,

using it only when fUSB is 48MHz is recommended).

Fig. 139 Block diagram of PLL circuit

PLL

fUSB

f(XIN)

fVCO

PLLCON

Division circuit

fSYN

(address 0FF816)

USBCON

(address 001016)

38K2 Datasheet(PDF) 114 Page - Renesas Technology Corp