38K2 datasheet(117/358 Pages) RENESAS

117 / 358 page

FUNCTIONAL DESCRIPTION

Rev.2.00

Oct 15, 2006

page 98 of 130

38K2 Group

REJ09B0338-0200

HARDWARE

Fig. 144 System clock generating circuit block diagram (single-chip mode)

Fig. 141 Ceramic resonator or quartz-crystal oscilltor circuit

Fig. 142 External clock input circuit

Fig. 143 Structure of MISRG

CIN

COUT

XIN

XOUT

Rd (Note)

Note : Insert a damping resistor if required.

The resistance will vary depending on the oscillator

and the oscillation drive capacity setting.

Use the value recommended by the maker of the

oscillator.

Also, if the oscillator manufacturer's data sheet

specifies that a feedback resistor be added external

to the chip though a feedback resistor exists on-chip,

insert a feedback resistor between XIN and XOUT

following the instruction.

XOUT

External oscillation circuit

Open

VCC

VSS

XIN

MISRG

(MISRG: address 0FFB16)

Oscillation stabilizing time set after STP instruction

released bit

0: Automatically set “0116” to Timer 1,

“FF16” to Prescaler 12

1: Automatically set nothing

Not used (indefinite at read)

Reset

PLL

1/8

1/4

1/6

fUSB

XIN

XOUT

fsio

fAD

1/8

1/4

1/2

1/1

1/2

FF16

0116

1/2

fvco

fSYN

USB clock selection bit

USB clock division

ration selection bits

System clock division

ration selection bits

Timer 1

Prescaler 12

Reset or STP

instruction

Timing

φ (internal clock)

STP instruction

WIT

instruction

STP instruction

Reset

Interrupt request

Interrupt disable flag l

System clock selection bit

38K2 Datasheet(PDF) 117 Page - Renesas Technology Corp

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