38K2 datasheet(121/358 Pages) RENESAS

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FUNCTIONAL DESCRIPTION

Rev.2.00

Oct 15, 2006

page 102 of 130

38K2 Group

REJ09B0338-0200

HARDWARE

Outline Performance (CPU Rewrite Mode)

CPU rewrite mode is usable in the single-chip or Boot mode. The

only User ROM area can be rewritten in CPU rewrite mode.

In CPU rewrite mode, the CPU erases, programs and reads the in-

ternal flash memory as instructed by software commands. This

rewrite control program must be transferred to a memory such as

the internal RAM before it can be executed.

The MCU enters CPU rewrite mode by applying 4.50 V to 5.25 V

to the CNVSS pin and setting “1” to the CPU Rewrite Mode Select

Bit (bit 1 of address 0FFE16). Software commands are accepted

once the mode is entered.

Use software commands to control program and erase operations.

Whether a program or erase operation has terminated normally or

in error can be verified by reading the status register.

Figure 147 shows the flash memory control register.

Bit 0 is the RY/BY status flag used exclusively to read the operat-

ing status of the flash memory. During programming and erase

operations, it is “0” (busy). Otherwise, it is “1” (ready). This is

equivalent to the RY/BY pin function in parallel I/O mode.

Bit 1 is the CPU Rewrite Mode Select Bit. When this bit is set to

“1”, the MCU enters CPU rewrite mode. Software commands are

accepted once the mode is entered. In CPU rewrite mode, the

Flash memory control register (address 0FFE16)

FMCR (Note 1)

RY/BY status flag

0: Busy (being written or erased)

1: Ready

CPU rewrite mode select bit (Note 2)

0: Normal mode (Software commands invalid)

1: CPU rewrite mode (Software commands acceptable)

CPU rewrite mode entry flag

0: Normal mode (Software commands invalid)

1: CPU rewrite mode

Flash memory reset bit (Note 3)

0: Normal operation

1: Reset

User area / Boot area select bit (Note 4)

0: User ROM area accessed

1: Boot ROM area accessed

Reserved bits (indefinite at read/ “0” at write)

Notes1: The contents of flash memory control register are “XXX00001” just after reset release.

2: For this bit to be set to “1”, the user needs to write “0” and then “1” to it in succession. If it is not

this procedure, this bit will not be set to ”1”. Additionally, it is required to ensure that no interrupt

will be generated during that interval.

Use the control program in the area except the built-in flash memory for write to this bit.

3: This bit is valid when the CPU rewrite mode select bit is “1”. Set this bit 3 to “0” subsequently after

setting bit 3 to “1”.

4: Use the control program in the area except the built-in flash memory for write to this bit.

CPU becomes unable to access the internal flash memory directly.

Therefore, use the control program in a memory other than inter-

nal flash memory for write to bit 1. To set this bit to “1”, it is

necessary to write “0” and then write “1” in succession. The bit can

be set to “0” by only writing “0”.

Bit 2 is the CPU Rewrite Mode Entry Flag. This flag indicates “1” in

CPU rewrite mode, so that reading this flag can check whether

CPU rewrite mode has been entered or not.

Bit 3 is the flash memory reset bit used to reset the control circuit

of internal flash memory. This bit is used when exiting CPU rewrite

mode and when flash memory access has failed. When the CPU

Rewrite Mode Select Bit is “1”, setting “1” for this bit resets the

control circuit. To set this bit to “1”, it is necessary to write “0” and

then write “1” in succession. To release the reset, it is necessary

to set this bit to “0”.

Bit 4 is the User Area/Boot Area Select Bit. When this bit is set to

“1”, Boot ROM area is accessed, and CPU rewrite mode in Boot

ROM area is available. In Boot mode, this bit is set to “1” auto-

matically. Reprogramming of this bit must be in a memory other

than internal flash memory.

Figure 148 shows a flowchart for setting/releasing CPU rewrite

mode.

Fig. 147 Structure of flash memory control register

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