38K2 datasheet(142/358 Pages) RENESAS

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FUNCTIONAL DESCRIPTION

Rev.2.00

Oct 15, 2006

page 123 of 130

38K2 Group

REJ09B0338-0200

HARDWARE

qStatus Register 1 (SRD1)

The status register 1 indicates the status of serial communica-

tions, results from ID checks and results from check sum

comparisons. It can be read after the SRD by writing the read sta-

tus register command (7016). Also, status register 1 is cleared by

writing the clear status register command (5016).

Table 15 lists the definition of each status register 1 bit. This regis-

ter becomes “0016” when power is turned on and the flag status is

maintained even after the reset.

Table 15 Status register 1 (SRD1)

Not verified

Verification mismatch

Reserved

Verified

SR15 (bit7)

SR14 (bit6)

SR13 (bit5)

SR12 (bit4)

SR11 (bit3)

SR10 (bit2)

SR9 (bit1)

SR8 (bit0)

Boot update completed bit

Reserved

Checksum match bit

ID check completed bits

Data reception time out

Reserved

“1”

Update completed

Match

Time out

“0”

Not Update

Mismatch

Normal operation

Definition

SRD1 bits

Status name

•Boot update completed bit (SR15)

This flag indicates whether the control program was downloaded

to the RAM or not, using the download function.

•Check sum consistency bit (SR12)

This flag indicates whether the check sum matches or not when a

program, is downloaded for execution using the download func-

tion.

•ID check completed bits (SR11 and SR10)

These flags indicate the result of ID checks. Some commands

cannot be accepted without an ID check.

•Data reception time out (SR9)

This flag indicates when a time out error is generated during data

reception. If this flag is attached during data reception, the re-

ceived data is discarded and the MCU returns to the command

wait state.

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